1. Field
Example embodiments relate to an electrode structure having at least two oxide layers and a non-volatile memory device having the same. Other example embodiments relate to an electrode structure having at least two oxide layers that more reliably switch and/or may operate without the use of additional devices and a non-volatile memory device having the same.
2. Description of the Related Art
The development of semiconductor memory devices having higher integration, higher operation speed and/or lower power consumption (e.g., a large number of memory cells per unit area) has been the focus of recent research.
A related art semiconductor memory device may include a plurality of memory cells. If the semiconductor device is a dynamic random access memory (DRAM), then a unit memory cell may include a switch and a capacitor. The DRAM may have higher integration and/or higher operation speed. If power to the DRAM is removed, then data stored in the DRAM may be lost.
Non-volatile memory devices may preserve stored data even after the power is removed. The non-volatile memory device may be a flash memory. The flash memory may have lower integration and/or lower operation speed compared to a DRAM.
Recent research on non-volatile memory devices focuses on magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase-change random access memory (PRAM) and resistance random access memory (RRAM).
The RRAM may utilize a resistance transition characteristic of a transition metal oxide wherein resistance varies according to a change in voltage.
FIG. 1 is a diagram illustrating a cross-sectional view of an electrode of a related art resistive random access memory device (RRAM).
An RRAM may be formed of a material having a variable resistance. The material having the variable resistance may be a transition metal oxide (TMO). The material may have a switching characteristic, thereby functioning as a memory device.
Referring to FIG. 1, a lower electrode 12, an oxide layer 14 and an upper electrode 16 may be sequentially formed on a substrate 10. The lower electrode 12 and the upper electrode 16 may be formed of a conductive material. The oxide layer 14 may be formed of a transition metal oxide having a variable resistance characteristic. The oxide layer 14 may be formed of zinc oxide (ZnO), titanium dioxide (TiO2), niobium oxide (Nb2O5), zirconium dioxide (ZrO2), or nickel oxide (NiO).
If the semiconductor device is a Perovskite-RRAM, then the switching material may be a Perovskite oxide (e.g., PCMO (PrCaMnO3) or Cr-STO(SrTiO3)). Memory characteristics of a Perovskite-RRAM may be established by applying voltage polarities to memory nodes of the Perovskite-RRAM using the principle of Schottky Barrier Deformation.